1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and, particularly, to a semiconductor integrated circuit device having a main memory portion and a sub-memory portion formed in a semiconductor substrate and a data transfer circuit provided between the main memory portion and the sub-memory portion.
2. Description of the Related Art
In general, a relatively low speed, inexpensive semiconductor device having large memory capacity, such as general purpose DRAM, is used as a main memory in a computer system.
In a recent computer system, an operating speed of a DRAM constituting a main memory is increased with increase of an operating speed of the system, particularly, of a MPU thereof. However, the operating speed of the DRAM is still insufficient and, in order to solve this problem, it is usual to provide a sub-memory between the MPU and the main memory. Such sub-memory is generally called as a cache memory and is constructed with a high speed SRAM or an ECLRAM.
The cache memory is generally provided externally of the MPU or within the MPU. In a recent work station or a personal computer, a semiconductor memory device composed of a DRAM constituting the main memory and a high speed SRAM as the cache memory which are formed on one and the,;, same semiconductor substrate is used. Japanese Patent Application Laid-open Nos. Sho 57-20983, Sho 60-7690, Sho 62-38590 and Hei 1-146187 disclose examples of such semiconductor memory. Such semiconductor memory is sometimes called as cache DRAM or CDRAM since it includes the DRAM and the SRAM functioning as the cache memory, etc. The cache memory can transfer data with respect to the DRAM and the SRAM bi-directionally. These prior arts have problems such as delay of data transfer operation in a case of cache mishit and techniques which solve such problem has been proposed. Examples of the proposed techniques are disclosed in Japanese Patent Application Laid-open Nos. Hei 4-252486, Hei 4-318389 and Hei 5-2872. In the techniques disclosed in these Japanese Patent Application Laid-open Nos., a latch or register function is provided in a bi-directional data transfer circuit between a DRAM portion and an SRAM portion, so that a data transfer from the SRAM portion to the DRAM portion and a data transfer from the DRAM portion to the SRAM portion can be done simultaneously and a speed of data transfer (copy back) at the cache mishit can be increased. This will be described with reference to Japanese Patent Application Laid-open No. Hei 4-318389 as an example. FIG. 92 shows schematically an example of a construction of a memory array portion of a CDRAM. In FIG. 92, a semiconductor memory device includes a DRAM array 9201 including dynamic memory cells, an SRAM array 9202 including static memory cells and a bidirectional transfer gate circuit 9203 for transferring data between the DRAM array 9201 and the SRAM array 9202. The DRAM array 9201 and the SRAM array 9202 are provided with row decoders and column decoders, respectively. Address Aa given to the row decoder and the column decoder of the DRAM and address Ac given to the row decoder and the column decoder of the SRAM are mutually independent and given through different address pin terminals. FIGS. 93 and 94 show a construction of the bi-directional transfer gate circuit 9203 in detail. According to this construction, the data transfer from SBL to GIO and the data transfer from GIO to SBL are made through different data transfer paths and it is possible to execute these data transfers simultaneously by functions of a latch 9302 and an amplifier 9306.
However, there are the following problems in the above mentioned CDRAM. First, since address pin terminals and control pin terminals are provided separately for the DRAM array and the SRAM array, the number of external pin; terminals is very large compared with that of a single DRAM. Therefore, there is no compatibility of a substrate, etc., on which the semiconductor memory is mounted, with respect to that of a usual DRAM, etc. Second, in the bi-directional transfer gate circuit, the number of circuits each having a area large enough to realize the above mentioned transfer is limited and, therefore, the number of transfer buses: is limited. As a result, the number of bits which can be transferred at once between the DRAM array and the SRAM array is limited to 16 bits. Further, the transfer buses are arranged in an area in which column selection lines are not arranged and the number of the transfer buses is limited by a width of the area. Generally, the smaller the number of bits transferred at once provides the lower the cache bit rate.
Japanese Patent Application Laid-open No. Hei 5-210974 discloses a technique in which address input signal pins of a CDRAM are made common for both a DRAM array and an SRAM array. FIGS. 95 and 96 show a construction of this technique. In this example, the second problem that the number of bits transferred at once between the DRAM array and the SRAM array is limited to 16 bits as in the CDRAM is left as it is. FIGS. 97 and 98 show a construction in which a memory capacity of an SRAM is increased in order to improve the cache hit rate. In this construction, however, the substrate compatibility is lost due to input pins for selecting SRAM cell and the second problem that the number of bits transferred at once between the DRAM cell array and the SRAM cell array is limited to 16 bits as in the CDRAM is solved.
As another example in this technical field, there is an EDRAM (Enhanced DRAM) which is a DRAM with a cache SRAM, as disclosed in, for example, EDN JAN. 5, 1995, pp. 46 to 56. An EDRAM shown in FIG. 99 is different in construction from a general purpose DRAM having the same memory capacity and has no substrate compatibility although a DRAM and an SRAM commonly use address input terminals. The number of bits transferred at once to the SRAM is the same as the number of sense amplifiers which are activated at once and, in this example, 512(xc3x974) bits are transferred at once. Although, in this construction of the EDRAM, the number of bits transferred at once is large, the SRAM thereof which holds data has a memory capacity of only 1 set (1 row) for bits to be transferred at once. Although the larger the number of bits transferred at on e generally provides the higher the cache hit rate, the cache mishit rate is increased since the EDRAM has cache memories of only 1 set (1 row) and, therefore, a sufficient speed-up of the whole system can not be achieved. In order to increase the number of sets (the number of rows) of the cache memories in the EDRAM, an SRAM register and a block selector, etc., must be additionally provided for every predetermined number of blocks of DRAM cell arrays, resulting in a substantial increase of the area occupied by the circuits.
Further, there is a recent problem of degradation of cache hit rate when there are access requests from a plurality of processing devices as shown in FIG. 100. When the CDRAM or the EDRAM is used as a main memory shown in FIG. 100 and there are access requests from a plurality of processing devices (memory masters), the cache hit rate is lowered and the speed-up of the whole system operation is restricted since the number of address requests of different sets (rows) may be increased.
With popularization of the system having a plurality of processing devices (memory masters), a memory portion which can respond to not access requests of one kind as in the conventional memory portion but access requests of a plurality of kinds. That is, a memory having a construction different from that of the conventional memory is required.
An object of the present invention is to provide a semiconductor integrated circuit device which, in order to achieve a high speed operation of a whole system without lowering cache hit rate even when there are access requests from a plurality of memory masters, includes a main memory portion and a sub memory portion capable of being assigned correspondingly to a plurality of access requests.
Another object of the present invention is to provide a semiconductor integrated circuit device having a main memory portion and a sub memory portion, an external terminal thereof being constructed similarly to a construction of that of the main memory portion.
A further object of the present invention is to provide a semiconductor integrated circuit device including a main memory portion and a sub memory portion, the number of bits capable of being transferred between the main memory portion and the sub memory portion at once and the number of sets thereof being optimized.
Another object of the present invention is to provide a semiconductor integrated circuit device including a main memory portion and a sub memory portion, in which a read/write operation of the sub memory portion and a data transfer operation between the main memory portion and the sub memory portion can be performed simultaneously.
In order to achieve the above objects, a semiconductor integrated circuit device according to the present invention includes a main memory portion constituted with memory cells arranged in a plurality of rows and in a plurality of columns and a sub memory portion constituted with memory cells arranged in a plurality of rows and in a plurality of columns, wherein at least one of address input terminals assigning rows or columns of said main memory portion and at least one of address input terminals assigning rows or columns of said sub memory portion are commonly used and a total number of address input terminals is equal to or smaller than the number of address input terminals assigning rows or columns of said main memory portion.
A semiconductor memory device according to another aspect of the present invention includes a first internal address signal generator circuit responsive to an address input terminal signal for generating first internal address signal, a second internal address signal generator circuit responsive to the first internal address signal for successively generating a second internal address signal during a burst mode operation and a circuit for selecting either of the first internal address signal or the second internal address signal and generating a third address signal by synchronizing the selected signal with an external clock signal or an external control signal.